LV/HV P-Well BCD[B]芯片工艺技术(2)的制程剖面结构

Structure of LV/HV P-Well BCD[B] Chip(2) and Process

LV/HV P-Well BCD[B]技术(2)能够实现低压5 V与高压100~700 V(或更高)兼容的BCD工艺。为了便于高低压MOS器件兼容集成,采用源区为硼磷双扩散形成沟道的具有漂移区的偏置栅结构的HV VDMOS器件。改变漂移区的长度,宽度,结深度以及掺杂浓度等可以得到高电压。采用MOS集成电路芯片结构设计、工艺与制造技术,依该技术得到了芯片制程结构。

LV/HV P-Well BCD [B] technology （2） can realize low voltage 5 V and high voltage 100-700 V （or higher） compatible BCD process. In order to facilitate compatible integration of high and low voltage MOSFETs, HV VDMOSFETs with bias gate structure in drift region were fabricated by double diffusion of boron and phosphorus in the source region. The high voltage can be obtained by changing the length, width, junction depth and doping concentration of the drift region. Based on the MOS IC chip structure design, process and manufacturing technology, the chip fabrication structure is obtained.