高速双模控制分频电路

A Circuit of Dual Modulus Prescaler

这是一种双模控制的高速分数预分频电路,它的主要特点是在不降低分辨率的基础上,通过预分频电路处理压控振荡器的高频信号,并利用优化后的半速率双模分频器结构,有效提高锁相环的参考频率,优化PLL的带宽,使其能有效控制环振VCO高频噪声,从而实现较好的相噪表现。利用该高速分数分频电路,在HLMC 55 nm低功耗工艺平台上实现了一款主频3 GHz,Tj<100 ps,Rj约2.5 ps的PLL,该PLL内置LPF电容,面积约1 000μm×300μm,IO电压3.3 V的条件下,功耗≤20 mW@3 GHz。

A circuit of Dual Modulus Prescaler is presented. The main characteristic is that the high-frequency signal of the VCO is processed by the pre-dividing circuit without reducing the resolution. The optimized half-rate dual-mode divider structure is used to effectively improve the reference frequency of the PLL. With the bandwidth of PLL, it can effectively control the high frequency noise of ring VCO and achieve better phase noise performance. Using this high-speed fractional frequency divider, a PLL with main frequency of 3 GHz, Tj 〈 100 ps and Rj about 2.5 ps is realized in the HLMC 55 nm low-power process. The PLL has built-in LPF capacitor with an area of about 1 000μm×300μm and an IO voltage of 3.3 V. The power consumption is less than 20 mW @ 3 GHz.