面向互连的综合策略

A wire-centered synthesis policy

VDSM (超深亚微米 )设计中互连线延迟已在电路延迟中起到决定性作用。在前期设计阶段考虑互连延迟问题已是当前研究的重要课题。建立以互连为中心的综合方法是当前的一个棘手问题 ,尚未有成熟的方法。提出一种面向互连延迟的综合策略 ,将前期设计定时规划 ,前期设计的线网规划和布局规划方法相融合 ,并在不同阶段给出了不同精度和复杂度的定时分析模型。另还给出了一个设计实例对综合策略予以了说明。

Interconnect delay has become a deterministic factor in VDSM design. How to deal with interconnect delay and establish an interconnect centered synthesis method is a key problem to be resolved. This paper presents a wire centered synthesis policy, combines timing planning, wire planning and IP based floor planning in early designs, and supplies several Boolean Process based delay analysis models. A design example is also given to illustrate the approach.