子阵级数字阵列模块综合测试系统设计与实现

Design and realization of integrated test system for digital array modules at subarray level

针对子阵级数字阵列模块的测试需求以及安全性、测试效率和系统集成等方面的难点,提出了收发测试分离、基于任务调度的并行测试、分级式发射测试开关网络设计与实现和基于大超噪比噪声源的接收通道噪声系数并行测试等总体设计思路,完成了系统硬件和软件设计,并搭建了完整的测试验证系统.经实验验证表明：在实现收发参数测试的基础上,子阵级数字阵列模块并行测试系统不仅提高了测试安全性,降低了系统集成难度,而且实现了4路发射通道和128路接收通道的并行测试,测试效率提高4倍.

For testing requirements of digital array modules at subarray level and the difficulties in security,test efficiency and system integration,this paper shows the general design idea including separation of sending and receiving test,parallel test based on task scheduling,the design and realization of the graded sending test switch-matrix,and receiving channel noise-factor parallel test based on the big excess noise ratio（ENR）,completes the design of system hardware and software,and makes the complete test and verification system.The test results show that the parallel test system for digital array modules not only can improve test security,but also can reduce difficulties in system integration,based on realizing the test of sending and receiving parameters.And test efficiency of the system improves 4 times based on parallel test with 4-transmission-channel and 128-reception-channel.