基于DDR3的群延迟模拟技术研究与实现

Research and implementation on the group delay simulation based on DDR3

针对通信、卫星等领域无线信道仿真器中秒级范围的群延迟模拟需求,提出了一种基于DDR3的高速海量FIFO设计实现方法。该方法采用＂乒乓＂操作利用Xilinx公司的XC7K325T芯片对内存颗粒MT41J256M16HA进行读写控制,读写操作交替进行,最终实现一入四出的高速海量FIFO设计,并通过ChipScope对该方法的数据流进行观测分析。仿真结果表明,该方法能够实现最大2s范围群延迟实时模拟,群延迟数目达到4条。该方法设计实现简单,资源消耗低,为无线信道模拟器的研制提供技术基础,具有重要参考价值。

Aiming at the requirements of group delay simulation with second level for wireless channel emulator in communications and satellite,an simulation method for high speed and great capacity FIFO based on double data rate3（DDR3）was provided.The design of a large scale FIFO was implemented with alternately reading and writing memory particles MT41 J256 M16 HA using XC7 K325 Tof Xilinx by ping-pong,which has one input port and four output ports.Finally,the data of the method was analyzed by Chipscope.The results show that the method can realize the real time simulation of group delay with maximum two second range,and the number of group path was four.the method have guidance significance and reference value for the research of wireless channel emulator which is simply and less resource consumption.