一种应用于SRAM型FPGA寄存器的容错设计

A fault-tolerant scheme applying to SRAM-based FPGA registers

寄存器作为SRAM型FPGA系统设计中的一个重要组成部分,容易受到太空环境中的高能粒子影响而发生软错误。三模冗余设计方法能够对寄存器进行容错防护,但带来大量的资源和功耗开销;针对此问题该文设计一种基于奇偶校验的双模冗余防护结构,以触发器为单位,利用FPGA查找表结构特点,将两位触发器作为一组进行容错设计,通过奇偶校验选择正确结果输出,能从细粒度方面对寄存器的数据位进行错误屏蔽。该方法于Xilinx Virtex?-6 FPGA中进行设计验证,实验结果表明该方法设计实现的寄存器相对于三模冗余设计方法能减少16.7%的触发器资源和50%的查找表资源。

Register is an important part of SRAM-based FPGA system that can be affected by soft errors caused by high energy particles in the space environment. Triple modular redundancy（TMR） can effectively achieve fault-tolerant protection for registers, but it brings a lot of resources and power consumption. A scheme of parity check dual modular redundancy（PC-DMR） is presented for such problems based on the structure of the LUTs in FPGAs with flip-flops as the unit. This scheme designs two flip-flops as a fault-tolerant pair, and it uses parity check to select the correct output and shield errors of register data from a fine-grained aspect.The scheme is designed and verified in Xilinx Virtex？-6 FPGA, and the results show that the proposed scheme can reduce 16.7% flip-flop resources and 50% LUTs resources relative to the triple modular redundancy design scheme.