一种采用DEM译码的16 bit高性能数模转换器的设计

Design of a 16 bit High Performance DAC by DEM Decoding

分析了目前分段电流舵数模转换器（DAC）在动态性能提升和芯片面积缩小等方面的局限性。提出了动态元件匹配（DEM）译码技术。设计了16 bit DAC中的DEM译码电路结构,分析了DEM译码技术的原理。对该16 bit DAC的动态性能等进行了详细仿真,并完成了整体版图设计。该DAC核心部分芯片面积仅为2. 2 mm^2。采用0. 18μm CMOS工艺完成了该DAC的加工和性能参数测试。在1 GHz采样率和100 MHz输入信号频率条件下,该DAC的无杂散动态范围约为67 dB,三阶互调失真约为76 dB,整体性能优于目前同类研究成果。

Limitations of dynamic performance promoting and chips area reducing for the segmented current-steering digital-to-analog converter（ DAC） were analyzed. A decoding technology called dynamic element matching（ DEM） was proposed. The DEM decoding circuit of 16 bit DAC were designed,and the principle of the DEM decoding technology were analyzed. The dynamic performances of the 16 bit DAC were simulated and the layout was designed. The core chip area of the DAC was only 2. 2 mm^2.The DAC was implemented By using 0. 18 μm CMOS process and the performance parameters were tested. The test results show that the DAC has a spurious free dynamic range about 67 dB and third-order inter-modulation distortion about 76 dB under the conditions of 1 GHz sample frequency and 100 MHz input signal frequency. The overall performance is better than other research results.