基于FPGA的SMS4算法实现及在线验证

Implementation and Online Verification of SMS4 Algorithm Based on FPGA

针对软件实现加解密算法占用主机系统资源较多、数据处理复杂、加密速度较慢的不足,提出一种硬件实现算法加密的方法。硬件加密具有成本低、加密速度快等优势,可以减轻CPU的负担以及提高服务性能。利用Vivado 2016.3开发工具和Verilog HDL硬件描述语言完成对SMS4算法的设计输入、功能测试、时序仿真,并封装为独立的IP核。在ZYNQ芯片上设计测试系统,通过ARM处理器调用自定义IP,完成算法在实际应用中的验证。结果表明:软件仿真验证,设计的算法功能正确,性能良好。在硬件实际测试过程中,算法运行正确,其工作最大频率为200 MHz,数据吞吐率达到800 Mbps。

Aiming at the problems of software encryption including the excessive use of host system resources,complex data processing, and slow encryption speed, a method of hardware encryption was proposed. Hardwareencryption has the advantages of low cost and fast encryption speed, which can reduce the burden of CPU andimprove service performance. By using Vivado 2016.3 development tools and Verilog HDL hardware descriptionlanguage, this paper completed the SMS4 algorithm design input, functional testing and timing simulation, andencapsulated them into independent IP core. The testing system was designed on ZYNQ chip, the user-definedIP was called through ARM processor and the verification of the algorithm in actual application was finished.The research results show that the designed algorithm has the correct function and good performance. In the ac-tual hardware test process, the algorithm is running correctly with the maximum working frequency of 200 MHzand the data throughput rate of 800 Mbps.