摘要
为顺应集成电路设计对器件提出更高性能要求的趋势,提出一种高性能折叠I型栅无结场效应晶体管,主要研究此类产品在不同栅极长度下的电学特性,讨论栅极的几何形状改变对器件性能产生的影响。通过与普通的双栅、三栅无结场效应晶体管的仿真结果的对比,突出FIG JL FET在电学性能上所具备的优势,并给出栅极设计参数的最佳优化方案。仿真实验结果表明,相比于其他的栅型结构,折叠I型栅无结场效应晶体管具有更低的反向泄漏电流,Ion-Ioff比也得到很大提升,而且几乎没有亚阈值的衰减。作为一款高性能器件,深具发展潜力。
In order to comply with the trend of higher performance requirements for devices inintegrated circuit design, a high-performance folded I-gate junctionless field effect transistor is proposed,which mainly studies the electrical characteristics of such products at different gate lengths and discussesthe influence of gate geometry changes on device performance. Compared with the simulation results ofcommon double-gate and three-gate junctionless FETs, the advantages of FIG JL FET in electricalperformance are highlighted, and the optimal scheme of gate design parameters is given. Simulationresults show that compared with other gate-type structures, folded I-gate junctionless FETs have lowerreverse leakage current, the Ion -Ioff ratio is greatly improved, and there is almost no subthresholdattenuation. As a high performance device, it has great development potential.
作者
高云翔
靳晓诗
GAO Yunxiang;JIN Xiaoshi(School of Information Science and Engineering,Shenyang University of Technology,Shenyang 110870,China)
出处
《微处理机》
2018年第5期11-14,共4页
Microprocessors