1G比特内嵌自检自修复DDR3 DRAM存储器芯片设计

1G Bit embedded ECC DDR3 DRAM Chip design

芯片采用45nm叠层电容工艺技术,采用旋转分区的对称存储体(BANK)芯片架构。内嵌自检测修复(ECC)电路设计可以用来检测和纠正出错的数据以提高阵列保持时间。芯片采用高可靠高性能单元阵列设计、高速输入输出接口电路设计等技术,设计开发高可靠、低功耗的兼容国际JEDEC-DDR3标准的1G比特DRAM芯片。

Chip uses 45 nm stack technology process and split bank architecture. Embedded ECC circuit can detect and correct error data, this method can dramatically improve the Cell retention time. This 1 G bit DDR3 chip is JEDEC DDR3 compatible. In order to achieve high reliability and low power target using below technique including high reliability and high performance array design; high speed low power IO.