基于FPGA的中断控制器设计

Design of FPGA-based Interrupt Controller

中断属于CPU的稀缺资源,在多外设系统中可能存在CPU的中断管脚数量少于外设数量的情况,需要将多路中断信号复用。在FPGA上使用Verilog HDL语言设计了一种中断控制器,可将32路中断信号复用成1路中断信号,减少对CPU中断资源的占用。该中断控制器使用简单,无需CPU对其进行配置,并具备中断信号锁存功能,在CPU进入中断服务程序后或处于中断屏蔽状态时,能够继续接收外设的中断信号,避免了中断信号的丢失。该中断控制器已在实际项目中应用,经验证其工作稳定可靠,达到了预期效果。

Interrupts, as the scarce resources of CPU, may exhibit the situation that the number of its interrupt pins is smaller than the number of peripherals in a multi-peripheral system, and this would require the multiplexing of multiple interrupt signals. An interrupt controller designed and implemented on the FPGA with Verilog HDL language, can multiplex the 32 interrupt signals into one interrupt signal, thus reducing the occupation of CPU interrupt resources. The interrupt controller, simple for use and requiring no configuration by CPU, has the function of interrupt signal latch, and can continue the receiving of peripheral interrupt signal after the CPU enters the interrupt service routine or is in the interrupt mask state, thus avoiding the loss of the interrupt signal. The interrupt controller is now applied in actual projects, and its stability and reliability verified, achieving the expected results.