基于FPGA的SAR数据源时序测试设计与实现

Design and Implementation of Testing Time Sequence in SAR Load Simulator Based on FPGA

针对星载合成孔径雷达(SAR)中数传分系统接收数据时序测试需求,设计一种SAR数据源系统,以FPGA构建数据处理单元,完成仿真数据存储、钟码关系合成以及BIT等功能,并设计通讯单元与输出接口单元完成人机交互与LVDS数据发送。同时,针对钟码关系拉偏测试需求,提出一种基于原语的延时单元设计,采用IODELAY原语通过时序约束实现正反向时钟拉偏功能。结果表明,系统具备时序拉偏测试功能,钟码关系调整范围可达-8～8 ns,步进1 ns,运行稳定。

In spaceborue synthetic aperture radar （SAR）, in allusion to the requirement of testing time sequence in data transmission sub- system, a new design of SAR load simulator system is implemented, which is based on FPGA. The system adopts FPGA as basic to build data processing unit, which is used to implement mass SAR simulation data storage, sequence synthesis of clock-data and BIT function. The man-machine and LVDS output interface are also implemented by communication unit and LVDS output unit. To meet the test require- ments of timing perturbation injection in data transmission subsystem, the delay unit based on IODELAY primitive, is designed by timing rules. Finally, the performance and robustness are assessed through the simulation and test, and the results show that the range of timing perturbation is from -8ns to 8ns with lns step, when delay unit is working in SAR load simulator system.