一种高分频下数字IC的低功耗逻辑综合方案

A Low Power Logic Synthesis Scheme for Digital IC with High Frequency Division

针对时钟分频系数较大的情况下,传统电路实现分频需要大量的寄存器,导致芯片功耗和面积增加的问题,提出了一种异步分频与门控时钟技术相结合的低功耗逻辑综合方案。基于HHGrace 0.11μm ULL工艺,通过采用所提出的方案和使用Design Compiler工具,完成了高精度Σ-ΔADC芯片中数字集成电路的逻辑综合。结果表明,使用该方案得到的数字IC的功耗为132.627μW。与传统方案相比,功耗降低了38.88%,面积缩小了2.7%。与门控时钟综合方案相比,功耗降低了25.43%。

In the case of larger clock divide factor,a large number of registers are needed to achieve the frequency division for traditional circuit,which causes the problems that the chip＇s power consumption and area are increased.So,a low power logic synthesis scheme combining the asynchronous frequency division and clock gating technology was proposed.Based on HHGrace 0.11μm ULL process,the logic synthesis for the digital integrated circuit of the high precision Σ-ΔADC chip was completed by adopting the proposed scheme and using Design Compiler tool.The results showed that the power consumption of the digital integrated circuit was 132.627μW.Compared with the traditional scheme,the proposed scheme＇s power consumption was reduced by 38.88% and the area was reduced by 2.7%.Compared with the clock gating synthesis scheme,the proposed scheme＇s power consumption was reduced by 25.43%.