基于互连线延时的SET脉冲宽度评估模型

A SET Pulse Width Evaluation Model Based on Interconnect Delay

研究了互连线延时对单粒子瞬态脉冲效应的影响。研究发现,随着互连线长度的增加,瞬态脉冲首先被展宽,在一定距离后,脉冲宽度衰减为零。基于此研究结果,提出了脉冲宽度随互连线长度变化的数学解析模型。在SMIC 130nm、90nm CMOS工艺下,采用Spice软件对应用该数学解析模型的多种器件进行验证。结果表明,该数学解析模型的计算值与仿真值误差最大为6.09%,最小为0.37%。该模型提高了单粒子瞬态脉冲宽度的评估准确度,可应用于单粒子瞬态脉冲效应的硬件加速模拟。

The influence of interconnect delay on SET injection pulse was studied.Simulation results showed that the transient pulse was broadened at first as the length of interconnect increased,and after a certain distance,the pulse width attenuated to zero.Based on the research results,a mathematical analysis model of pulse width with the length of interconnection was proposed.The validity of the proposed model was verified by different device types in SMIC 130 nm and 90 nm CMOS technology.Spice simulation results demonstrated that the maximum error between theoretical and simulated results was 6.09% and the minimum error was 0.37%.The model improved the accuracy of SET pulse width evaluation and could be used for hardware acceleration simulation of SET.