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一种600V高压超结VDMOS结构设计与优化

Design and Optimization of 600V High Voltage Super-Junction VDMOS
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摘要 基于电荷补偿原理的超结VDMOS(Super-Junction VDMOS,SJVDMOS)器件,比传统的VDMOS具有更低的比导通电阻,更高的击穿电压.文中详细介绍了超结VDMOS元胞设计步骤,之后借助TCAD仿真对超结VDMOS的击穿电压和比导通电阻进行了深入优化,探究了电荷不平衡、漂移区厚度、衬底反向扩散以及表面结构等对击穿电压和比导通电阻的影响.对元胞结构的优化使得超结VDMOS由最初的击穿电压为587V,比导通电阻为7.27mΩ·cm2,优化到最终的击穿电压为662.5V,比导通电阻为6.85mΩ·cm2,性能得到明显改善. Based on the charge compensation principle,the super junction VDMOS(Super-Junction VDMOS,SJVDMOS)device has lower specific on-resistance and higher breakdown voltage than the traditional VDMOS.This paper introduces the super junction VDMOS cell design steps in detail.The TCAD is used to simulate the breakdown voltage and the specific on-resistance of super-junction VDMOS.The effects of charge imbalance,drift zone thickness,substrate back diffusion and surface structure on the breakdown voltage and specific on-resistance are investigated.The optimization of cell structure improves the performance of the super junction VDMOS obviously.The initial breakdown voltage improves from 587 Vto 662.5 V,and the specific on-resistance declines from 7.27 mΩ·cm^2 to 6.85 mΩ·cm^2.
作者 王荣超 王立新 邢心润 王琳 罗家俊 WANG Rong-chao;WANG Li-xin;XING Xin-run;WANG Lin;LUO Jia-jun(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100029,China;Key Laboratory of Silicon Device Technology,Chinese Academy of Sciences,Beijing 100029,China)
出处 《微电子学与计算机》 CSCD 北大核心 2018年第11期67-72,共6页 Microelectronics & Computer
关键词 超结VDMOS 比导通电阻 击穿电压 结构优化 SJVDMOS specific on-resistance breakdown voltage structural optimization
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  • 1Lorenz L, Deboy G, Knapp A, et al.COOLMOS-a New Milestone in High Voltage Power MOS[A].Proceedings of llth ISPSD[C].1999:3-10.
  • 2Leo Lorenz.CoolMOS-A New Approach Toward and Idealized Power Switch[C].Proc. EPE '99 Conf., 1999.
  • 3CHEN Xingbi.Theory of the Switching Response of CB MOST[J].Chinese Journal of Electronics,Jan. 2001,10( 1 ) : 1-6.
  • 4陈星弼.ZL01141993.一种制造含有复合缓冲层半导体器件的方法[P].2004.
  • 5Xingbi Chen.Method of Manufacturing Semiconductor Device having Composite Buffer Layer. US 7192872 B2,2007.
  • 6陈星弼.ZL93115356,具有异型掺杂岛的半导体耐压层[P],1997.
  • 7Xingbi Chen.Voltage Sustaining Layer with Opposite-Doped Islands for semiconductor Power Devices,US 6635906 B1,2003.
  • 8Xingbi Chen,Semiconductor High- voltage Devices,US 6936867 B2,2005.
  • 9Xingbi Chen Semiconductor High-voltage Devices,US 7227197 B2, 2007.
  • 10Xingbi Chen.Semiconductor High-voltage Devices, Appl. No. 11/365,223,2006.

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