LV/HV N-Well BCD[B]技术(2)的芯片与制程剖面结构

Structure of Chip and Process in LV/HV N-Well BCD[B] Method(2)

LV/HV N-Well BCD[B]技术(2)能够实现MOS器件低压5 V与高压100～700 V (或更高)和双极型器件低压5 V与高压30～100 V兼容的BCD工艺。为了便于高低压器件兼容集成,采用源区为硼磷双扩散形成沟道的具有漂移区的偏置栅结构的HV LDMOS器件,并同时形成HV双极型器件。改变漂移区的长度,宽度,结深度以及掺杂浓度等可以得到不同的高电压。采用芯片结构设计、工艺与制造技术,依该技术得到了芯片制程结构。

LV/HV N-Well BCD [B] technology（2） can realize low-voltage 5 V and highvoltage 100～700 V（or higher） of MOS devices and low-voltage 5 V and high-voltage 30～100 V compatible BCD process of bipolar devices. In order to facilitate compatible integration of high and low voltage devices, HV LDMOS devices with bias gate structure of drift region were fabricated by double diffusion of boron and phosphorus in the source region. It forms HV bipolar devices simultaneously. Different high voltage can be obtained by changing the length, width, junction depth and doping concentration of the drift region. The technology of chip structure design, process and manufacturing technology is adopted.