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面向目标的主动绕障PCB布线算法 被引量:1

Goal-Oriented PCB routing algorithm for active wound Barrier
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摘要 本文提出了面向目标的主动绕过布线障碍物的自动布线算法,它是一种无网格布线算法,因此继承了无网格算法的优点,PCB板面信息只与器件和其他障碍物有关,信息复杂度取决于PCB电路板本身,而不受人为定义的额外信息所影响。该算法可适用于复杂不规则的任意形状障碍物,引入主动绕过障碍物的方法,使得布线更有主动性,从而降低了探索的盲目性,普遍减少了探索的次数,另外也采取了一定的优化办法,使得布线具有较少的拐点和较短的布线距离。 A goal-oriented automatic routing algorithm for actively bypassing routing obstacles is proposed. It is a gridless routing algorithm, so it inherits the advantages of meshless algorithm. The PCB panel information is only related to devices and other obstacles. The information complexity depends on the PCB circuit board itself and is not affected by the additional information that is defined artificially. The algorithm can be applied to complex and irregular obstacles with arbitrary shapes. The method of actively bypassing obstacles is introduced to make routing more active, thus reducing the blindness of exploration and generally reducing the number of explorations. In addition, some optimization methods are adopted to make the cabling have less inflection points and Shorter wiring distance.
作者 宋谦 路林吉 Song Qian;Lu Linji(l.Department of Automation,Shanghai Jiaotong University,Shanghai,20003;Apis(Shanghai)Communications Technology Co.,Ltd.,Shanghai,200333)
出处 《电子测试》 2018年第22期44-45,共2页 Electronic Test
关键词 自动布线 无网格布线 主动绕障 面向目标 automatic wiring netless cabling active obstacle winding goal-oriented
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  • 1陈国龙.一种自动布线方法──多级线探索法[J].计算机辅助设计与图形学学报,1994,6(2):136-142. 被引量:1
  • 2刘军.浅谈算法设计与算法时间复杂度.电脑知识与技术,2008,(5):878-879.
  • 3Toumazou C, Makris C A. Analog IC design automation: Part Ⅰ- automated circuit generation : new concepts and methods [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995, 14(2) : 218-238
  • 4Hamour M, Saleh R, Mirabbasi S, et al. Analog IP design flow for SoC applications [C] //Proceedings of the 2003 International Symposium on Circuits and Systems, Bangkok, 2003:Ⅳ676-Ⅳ679
  • 5Tang D D, Diaz C H, Chao C P, et al. Foundry technology for 130nm and beyond SoC [C] //Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, San Jose, 2003: 343- 350
  • 6Rijmenants J, Schwarz T, Litsios J, et al. ILAC: an automated layout tool for analog CMOS circuits [C]//Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, San Jose, 1988:7.6.1-7.6.4
  • 7Mogaki M, Naoki K, Chikami Y, et al. LADIES: an automatic layout system for analog LSI's [C] //Proceedings of the International Conference on Computer-Aided Design, Santa Clara, 1989:450-453
  • 8Malavasi E, Sangiovanni-Vincentelli A. Area routing for analog layout [J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993, 12(8): 1186-1197
  • 9Cohn J M, Garrod D J, Rutenbar R A, et al. KOAN/ ANAGRAM Ⅱ: new tools for device-level analog placement and routing [J]. IEEE Journal of Solid-State Circuits, 1991, 26 (3) : 330-342
  • 10Lampaert K, Gielen G, Sansen W. Analog layout generation for performance and manufacturability [M]. Boston: Kluwer Academic Publishers, 1999:121-122

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