数字电路端口驱动能力实验项目的设计

Design of Digital Circuit Port Drive Capability Experiment Project

电子技术的快速发展催生了多达几十种的I/O接口电平标准,一个电子系统中可能同时存在多种逻辑电平。现代数字系统的设计实现也不再是由纯数字的、中小规模的芯片连接搭建而成,而是以FPGA为核心进行高级行为描述、仿真正确后下载得到。学生学习过程中理论多、软的多;在做实际项目时,会遇到程序、逻辑关系正确,但负载器件却不能正常工作的情况,及工程调试中的类似故障。本实验项目是在新工科背景下,通过探究数字电子技术中端口的驱动能力,理解软硬结合及器件的互联,也为学生的创新实践能力打下坚实的基础。

The rapid development of electronic technology has spawned up to dozens of I/O interface level standards, and there may be multiple logic levels in an electronic system. The design of the modern digital system is no longer a small and medium-sized pure digital chip connection, instead, it is the core of FPGA, the use of high-level language to describe the behavior, the simulation after the download. In the course of student learning, there are many theories and software. However, in the actual project, the logical relationship may be correct, but the load device cannot work normally. A similar failure may happen in the engineering debugging. The project is based on the new engineering background to explore the driving capacity of the digital electronic technology. It also lays a solid foundation for the students’ innovation and practical ability.