5Macpherson K N, Stewart R W. Low FPGA area multiplier blocks for full parallel FIR filters [C]//Proceedings of IEEE International Conference on Signal Processing. [S.l. ]:IEEE, 2004: 247-254.
6Jang Y, Yang S. Low-power CSD linear phase FIR filter structure using vertical common sub-expression[J]. Electronics Letters, 2002, 38(15): 777-779.
7Uwe Meyer - Baese. Digital Signal Processing with Field Programmable Gate Arrays. Tsinghua University Press, 2006.
8Sanjit K Mitra. Digital Signal Processing: A Computer- Based Approach. Tsinghua University Press,2004.
9Michael D Ciletti. Advanced Digital Design with the Verilog HDL[M]. Publishing House of Electronics Industry,2007.