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A Hierarchical Reconfiguration Strategy for Bus-Based Multiprocessors

A Hierarchical Reconfiguration Strategy for Bus-Based Multiprocessors
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摘要 A method of providing redundancy to a class of bus-based multiprocessor arrays is discussed.The reconfiguration is hierarchical,providing global spare replacement at the array level and local reconfiguration within the spare block.Results of yield analysis performed on a 32 processor array are pres- ented. A method of providing redundancy to a class of bus-based multiprocessor arrays is discussed.The reconfiguration is hierarchical,providing global spare replacement at the array level and local reconfiguration within the spare block.Results of yield analysis performed on a 32 processor array are pres- ented.
机构地区 VLSI Design Laboratory
出处 《Journal of Computer Science & Technology》 SCIE EI CSCD 1990年第2期175-186,共12页 计算机科学技术学报(英文版)
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