期刊文献+

An efficient VLSI implementation of H.264/AVC entropy decoder 被引量:1

An efficient VLSI implementation of H.264/AVC entropy decoder
下载PDF
导出
摘要 This paper proposes an efficient H.264/AVC entropy decoder.It requires no ROM/RAM fabrication process that decreases fabrication cost and increases operation speed.It was achieved by optimizing lookup tables and internal buffers,which significantly improves area,speed,and power.The proposed entropy decoder does not exploit embedded processor for bitstream manipulation, which also improves area,speed,and power.Its gate counts and maximum operation frequency are 77515 gates and 175MHz in 0.18um fabrication process,respectively.The proposed entropy decoder needs 2303 cycles in average for one macroblock decoding.It can run at 28MHz to meet the real-time processing requirement for CIF format video decoding on mobile applications. This paper proposes an efficient H.264/AVC entropy decoder.It requires no ROM/RAM fabrication process that decreases fabrication cost and increases operation speed.It was achieved by optimizing lookup tables and internal buffers,which significantly improves area,speed,and power.The proposed entropy decoder does not exploit embedded processor for bitstream manipulation, which also improves area,speed,and power.Its gate counts and maximum operation frequency are 77515 gates and 175MHz in 0.18um fabrication process,respectively.The proposed entropy decoder needs 2303 cycles in average for one macroblock decoding.It can run at 28MHz to meet the real-time processing requirement for CIF format video decoding on mobile applications.
出处 《Journal of Measurement Science and Instrumentation》 CAS 2010年第S1期143-146,共4页 测试科学与仪器(英文版)
基金 sponsored by ETRI System Semiconductor Industry Promotion Center,Human Resource Development Project for SoC Convergence.
关键词 VIDEO CODING H.264/AVC ENTROPY CODING VARIABLE len video coding H.264/AVC entropy coding variable length coding CAVLC
  • 相关文献

参考文献6

  • 1Chang,H.C,Lin,C.C,Guo,J.I.A Novel Low-Cost High-Performance VLSI Architecture for MPEG-4 AVC/H.264 CAVLC Decoding[].IEEE International Symposium on Circuits and Systems.2005
  • 2Lee,D.J,Jeong,Y.J.VLSI architecture design of CAVLC entropy encoder/decoder for H.264/AVC[].Journal of Korea Information and Communications Society.2005
  • 3Alle,M,Biswas,J,Nandy,S.K.High Performance VLSI Architecture Design for H.264 CAVLC Decoder[].IEEE International Conference on Application-specific SystemsArchitectures and Processors.2006
  • 4Oh,M.S,Lee,W.J,Kim,J.S.DESIGN OF HIGH SPEED CAVLC DECODER FOR H.264/AVC[].IEEE Workshop on Signal Processing Systems.2007
  • 5Joint Video Team(JVT) of IS0/IEC MPEG and ITU-T VCEG.Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification(ITU-T Rec.H.264|ISO/IEC 14496-10 AVC)[].ITU-T RecH/ISO/IEC - AVC)JVT-G.2003
  • 6Horowitz M,Joch A,Kossentini F,et al.H.264/AVC Baseline Profile Decoder Complexity Analysis[].IEEE Transactions on Circuits and Systems for Video Technology.2003

同被引文献3

引证文献1

二级引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部