基于FPGA的1553B总线同步头获取技术

Research on Synchronization Head for 1553B Bus Technology Based on FPGA

准确获取同步头是MIL-STD-1553B总线数据帧解码的第一步,通过对1553B总线字同步头形态进行分析,列举了同步头的所有可能形态,基于1553B总线协议,明确了同步头获取和采样的原理和过程;1553B总线数据通过专门的总线接口接收,输入到可编程逻辑器件FPGA中,使用Verilog HDL硬件描述语言,对波形进行预处理以消除毛刺,并对同步头进行采样处理,最后使用ISE实现了结果仿真;该同步头获取方法为其后的信息解码创造了良好条件,丰富和完善了对1553B总线监测系统的研究。

Accurately acquiring the synchronization head of MIL-STD-1553 B bus is the first step in the da-ta frame decoding. Through analyzing 1553B bus word synchronization head shape,the synchronization head of all possible forms were enumerated. Based on 1553B bus protocol,the process and the principle of sampling were clear. 1553B bus data was received through specialized bus interface and input into the pro-grammable logic device FPGA,using Verilog HDL hardware description language,the waveform prepro-cessing to remove burrs and the synchronization head sample processing. Finally we used the ISE to realize the simulation results. This method has created favorable conditions for the following information decoding and enriches the study of 1553B bus monitor system.