基于PLC的SD加法器在DSP领域中的应用

A Novel Signed-Digit Adder Based on PLD Used in DPS

本文提出了一种以SD(Singed_Digit)数表示的求和计算方法 ,克服了传统的二进制数表示求和过程中产生的进位对运算速度的限制。并在此基础上应用硬件描述语言 (VHDL)设计实现了基于可编程逻辑器件 (PLD)的SD加法器 ,简化了求和运算过程。实验证明 ,通过这种算法可得到运算速度高、电路结构简单的高速加法器。以满足数字信号处理 (DSP)系统的高性能要求。

A novel additive arithmetic algorithm using radix-2 signed-digit(SD) number representation is presented.It can resolve the problem that speed of arithmetic operations is limited by carry propagation in a conventional binary system.In this paper,a p-digit radix-2 SD number system is introduced to simplify the addition operation.The design and simulation results of some addition circuits show that simple high speed adders can be obtained by the presented algorithms.