低功耗内建自测试的参数优选

Parameter Optimization of Low Power BIST

提出了面向低峰值功耗进行 BIST参数优化的问题 ,给出了相应的种子选取算法 .实验结果表明该方法不需要额外的硬件开销 。

With the fast growing portable electronics market and stricter requirement of the wafer test, the power consumption problem of built in self test (BIST) has attracted more and more attention. In this paper, a parameter optimization algorithm that can lower the peak power during test application has been proposed. Experiment results show that peak power is reduced considerably with no extra silicon overhead of test logic on the condition that fault coverage is guaranteed.