CMOS Design of Ternary Arithmetic Devices Wu Xunwei Dept.of Electronic Engineering,Hangzhou University,Hangzhou 310028F.P rosser Dept.of Computer Science,Indiana University,U.S.A.
CMOS Design of Ternary Arithmetic Devices Wu Xunwei Dept.of Electronic Engineering,Hangzhou University,Hangzhou 310028F.P rosser Dept.of Computer Science,Indiana University,U.S.A.
摘要
This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.Compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.
This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.Compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.
基金
Project supported by the National Natural Science Foundation of China.
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1Air Multiplier风扇[J].新潮电子,2009(11):213-213.
-
2王海燕,欧阳丹彤,张永刚,张良.结合look-ahead值排序的自适应分支求解算法[J].通信学报,2013,34(6):102-107. 被引量:1
-
3付跃文,仲伟波.基于多词汇树的对话语音识别搜索策略[J].微计算机信息,2007(03X):262-264.
-
4运算器与逻辑部件[J].电子科技文摘,2002,0(9):114-115.
-
5Mojtabavi Naeini Mahshid,Navi Keivan.A New Full-Adder Based on Majority Function and Standard Gates[J].通讯和计算机(中英文版),2010,7(5):1-7.
-
6李秋莹,陈永辉,邱绮文,林志敏.Unified Parallel Systolic Multiplier Over GF(2^m)[J].Journal of Computer Science & Technology,2007,22(1):28-38.
-
7胡明,彭来献,兰明蛟,宋孝先.基于VxWorks网络协议栈的数据采集协议设计[J].测控技术,2007,26(12):45-47. 被引量:2
-
8ZHANG LiXian,SUN RuiYong,GAO XiaoShan,LI HongBo.High speed interpolation for micro-line trajectory and adaptive real-time look-ahead scheme in CNC machining[J].Science China(Technological Sciences),2011,54(6):1481-1495. 被引量:17
-
9Long Yindong Qiao Weimin Jing Lan.23 Bit's Floating-point Numbers' fast Multiplier[J].近代物理研究所和兰州重离子加速器实验室年报:英文版,2007(1):140-140.
-
10郑东裕,孙岩,李少青,方粮.A 485ps 64-Bit Parallel Adder in 0.18μm CMOS[J].Journal of Computer Science & Technology,2007,22(1):25-27. 被引量:1