基于CPLD和VHDL的CCD驱动时序电路设计

Design of Colorized Liner CCD Driving Sequence Base on CPLD and VHDL

本文描述了彩色线阵CCD-TCD2252D驱动电路的时序关系,介绍了一种基于CPLD和VHDL的CCD驱动时序电路设计方法。采用Quartus II9.0对所设计的驱动时序进行仿真,给出了驱动电路的设计结果和时序仿真图,以及实际波形图。实验验证了这种时序电路的可行性,满足CCD的驱动时序要求。

By analyzing the driving sequential relationship of colorized liner CCD-TCD2252D, a design method of driving circuit based on VHDL language and CPLD is presented as well as the simulated and the practical results of the driving circuit, adopting QuartusII9.0 to make simulation analysis to its driving sequence. The results indicate that the design is feasible and precise. Moreover, they prove that the designed circuit can meet the working requirement of CCD.