Dielectric Integration for Sub-Micron High Performance Integrated Circuits

With the continued scaling of semiconductor devices, dielectric proceesses arefacing some major technological challenges. Many issues are being raised including high as-pect ratio gap fill, planarization, low dielectric constant, multilevel intereonnects integra-tion and cost-of-ownership. In this paper, the issues related to dielectric deposition and in-tegration at various stages of the device fabrication including active area isolation, poly/metal insulation, inter-metal and intra-metal insulation and device passivation are dis-cussed. Current avallable technologies such as ozone/TEOS are eompared with high densityplasma CVD and spin-on glass (SOG). The integration of chemical mechanical polishing(CMP) with various dielectric deposition schemes, and the benefits of CMP for all interlev-el dielectric planarization will be highlighted. The need for low dielectric constant materichfor sub-half ndcron technologies and the use of fow dielectric constant materials for intermet-al applications in combination with simultaneous formation of via plug and metal intercon-nects with CMP planarization are highlighted.