基于FPGA的差错控制编译码系统设计

FPGA-based Design for Signal Channel Encoding/Decoding System of Error Detection and Correction

利用FPGA开发板,结合Verilog-HDL硬件描述语言设计出了差错控制的信道编译码系统,应用于16位的数字语音信号和混沌信号的通信平台。实验表明此设计可以提高通信系统的可靠性。

This project describes the method that implement the signal encoding/decoding system based on Error Detection and Correction in the FPGA development board by the Verilog-HDL hardware description language,then Applies it in 16 byte digital voice signal and the chaos signal communications platform.The result of testing shows that the system reliability is improved.