基于FPGA的32位数学运算库IP核设计实现

IP Core Design Realization of 32-bit Arith_Lib Based on FPGA

为了在嵌入式CPU中实现数学运算,设计了一个32位数学运算库IP核,以提高运算能力,基于该思想详述了系统架构及各功能模块的实现。并进行了仿真和测试,通过实验在基于OR1200的SOC平台上做了FPGA验证,结果表明经过本模块加速后数学运算的处理速度可行有效,达到了设计目标。

To realize the arithmetic computing in the embedded CPU,a IP core of 32-bit arith_lib is designed to save time,based on the idea,the system architecture and the functional modules are described detailedly.The simulation and test are implemented for the functional modules,and the FPGA verification is done on the SOC platform based on OR1200.The results show that the processing speed of arithmetic computing through the module speeding is actractive for use,met the expectation.