基于Verilog和VHDL的状态机设计技术

Design Technology of State Machine Based on Verilog and VHDL

对于数字逻辑工程师来说,设计一个同步有限状态机(FSM)是一项很常见的任务。该论文讨论了若干关于设计有限状态机方面的问题,包括用于状态分配的状态编码方法,状态机的输入输出等等。

Designing a synchronous finite state machine(FSM) is a common task for a digital logic engineer.This paper will discuss a vari ety of issues regarding FSM design,including status coding method for status assignment,input and output of state machine.