摘要
该文运用VHDL硬件描述语言进行数字频率计设计,频率计主要通过闸门控制电路产生计数周期为1s,清零周期为0.5s,2s为一个周期的测量信号频率。并通过计数器记录频率值,最后通过数码显示电路显示被测信号频率值。该文设计一个6位频率计,可以测量1~999999Hz的信号频率。
In this paper, by using VHDL hardware description language to design the digital frequency meter, frequency meter is mainly through the gate control circuit to produce cycle count as 1 s, reset cycle is 0.5 s, 2 s for a cycle of the signal frequency measurement. And through the counter recorded frequency values, and finally through the digital display circuit measured signal frequency value. This paper design a six bit frequency meter, 1~999999 Hz signal frequency can be measure.
出处
《电脑知识与技术（过刊）》
2014年第7X期4911-4912,4930,共3页
Computer Knowledge and Technology
