基于扫描链二次排序组合的低功耗测试方法

Low Power Test Method Based on Scan Chain Two Times Reordering and Combination

减少SoC的测试时间是降低测试成本的有效方法。提出一种二次排序组合的扫描链平衡算法以减少IP核测试时间。算法首先对内部扫描链按升序排列,然后对其进行mod n(封装后扫描链的条数)划分,得到n个余数序列,将余数为0的序列按降序排列,与其它余数序列组合成新的序列;对新序列再进行一次mod n划分,再次得到n个余数序列,最后对各余数序列分别求和,求和的结果即为n条扫描链封装后的扫描链长度。在ITC’02基准电路上的实验结果表明,该算法能有效地缩短IP核测试时间。

Reducing SoC test time is an effective way to reduce testing costs.This paper proposes a scan chain balance algorithm based on two times reordering and combination for minimizing IP testing time. Firstly, the internal scan chains in ascending order, then its mod n(the number of packaged scan chain) division, get the n remainder sequence, the remainder of the sequence 0,in descending order, and other than a few sequences combined into a new sequence; once again for the new sequence mod n is divided to obtain a sequence of residues n again, and finally the remainder of the respective sequences are summed, the result is the sum of the length n of the scan chain after scan chains package.Experimental results on ITC'02 benchmark circuits show that the method can effectively reduce the test time.