LDPC译码器中SISO模块的高层次综合实现

Implementation of SISO Module in LDPC Decoder with High-Level Synthesis Tool

日益增长的硬件设计复杂度和越来越短的芯片研发周期给集成电路设计带来了极大的挑战。通过更高抽象层实现硬件设计自动化的方法是解决问题的关键。Vivado TM High-Level Synthesis(HLS)是Xilinx公司发布的高层次综合工具。针对信道编解码LDPC译码器芯片的核心模块—软输入软输出(Soft-Input Soft-Output,SISO)模块,采用HLS设计方法进行了基于C语言模型的实现。HLS的综合结果能与手工使用Verilog实现的性能接近,但明显缩短了设计时间。

The increasing complexity of hardware and decreasing time of development brings challenges to integrated circuit de-sign. High-level synthesis-based design automation is the key to solve the problem. VivadoTMHigh-Level Synthesis is a high-levelsynthesis tool from Xilinx Inc. Targeting the Soft-Input Soft-Output(SISO) module which is the core unit of LDPC decoder, HLSmethodology is applied by programming the SISO module in C. The synthesis result shows that HLS based design achieves similarhardware efficiency as compared to the manually coded design using Verilog, while significantly reducing the design effort.