AES-128算法的集成电路设计方法

The Integrated Circuit Design Method of AES-128 Algorithm

该文从降低资源消耗的目标出发,提出了AES-128算法的集成电路设计方法。使用Verilog HDL语言进行RTL级建模,采用Model Sim工具进行功能仿真,完成了FPGA验证,综合结果表明本设计实现了降低硬件资源消耗的目标。

This article embarks from the target to reduce the consumption of resources, and puts forward the integrated circuit de-sign method of AES- 128 algorithm. Using Verilog HDL modeling the RTL, Model Sim tool improving the functional simulation,completing the FPGA verification, the design realized the aim to reduce the consumption of hardware resources.