基于VHDL语言的数字频率计电路的设计

Design of Digital Frequency Meter Based on VHDL

本文介绍了VHDL语言及其基本特点,讨论了VHDL语言在EDA中的诸多优点,并介绍了基于MAX+PLUSⅡ开发软件,用VHDL语言设计频率计的一种方法,最后给出频率计电路的时序仿真波形,以验证结果与设计指标之间的一致性是否满足实际要求。

This paper introduces the VHDL language and its basic characteristics,and a design method of digital frequency meter based on MAX+PLUSII and VHDL language. Finally,it gives the timing simulation waveform of the frequency meter to verify whether the consistency between the results and the design specifications meet the actual requirements.