14 nm工艺下基于CUPF的数字IC低功耗物理设计

Digital IC physical design low power implement based on CUPF flow under 14 nm process

随着集成电路生产工艺的迅速发展,功耗作为芯片质量的重要衡量标准引起了国内外学者越来越多的重视和研究。当晶体管的特征尺寸减小到纳米级时,其泄露电流的增加、工作频率的提高和晶体管门数的攀升极大提高了芯片的功耗。同时,传统的基于UPF(Unified Power Format)的低功耗设计流程存在着效率低、可修复性差等缺点。针对以上问题,以14 nm工艺下数字芯片fch_sata_t模块为例,简要介绍了全新的基于CUPF(Constant UPF)的低功耗物理设计流程,利用门控电源和多电源电压等技术对芯片进行低功耗设计。最终,通过Synopsys旗下PrimetimePX提供功耗分析结果,证明了芯片功耗满足设计要求。

With the rapid development of integrated circuit manufacturing process, power consumption as an important measure of the chip quality caused more and more attention and research by scholars both at home and abroad. When the sizes of transistor feature decrease to nanoscale, the increase of leakage current, the improvement of working frequency and the large amounts of transistor gates improve the power consumption of the chip. At the same time, the traditional low-power technology based on the UPF( Unified Power Format) process exists certain disadvantages such as low efficiency and poor restore sexual. To solve above problems, this paper takes digital chip fch_sata_t which under 14 nm technology as an example and briefly introduces a new physical design flow based on CUPF( Constant UPF). Decreasing power consumption by using power switch cells and multiple voltage supply technology for low power design of chip, etc. In the end, through PrimetimePX carry out consumption analysis results,proved that the chip power consumption to satisfy the design requirements.