模拟集成电路模块版图的生成系统

A module generator environment for analog integrated circuits

介绍了模拟集成电路模块版图的开发系统。系统用高效的过程化版图描述语言构造模拟模块,编译产生与工艺及应用无关的模块版图生成器。系统的网络识别和模块内布线功能自动完成模块网络的完全连通,基于优选的电气特性驱动版图生成,提高设计可靠性。该系统已辅助设计出多个高性能集成运算放大器、模拟开关等芯片版图。

This paper describes a novel module generator environment for the automatic layout development of analog integrated circuits. With the natural layout procedural description language, analog modules are written in a technology and application independent way. The wiring inside modules is automatically implemented to ease their construction. The optimal or near optimal interconnections are found for the modules with separate multipin nets. Electrical properties are thoroughly regarded for the control of module construction in order to make circuits work reliably. Several high quality optional amplifiers and analog switches have been designed with the help of this environment.