摘要
针对SAT问题的复杂性及求解速度缓慢的问题,采用可重构器件FPGA设计,实现了静态回溯搜索算法SAT问题并行处理器,提出了研制动态SAT并行处理器的设想.
Due to the complexity of the SAT problem, the speed of solving the SAT problem with software method is very slow. Using the reconfigurable characteristic and the ability of processing data parallelly of the FPGA, the static backtrack search algorithm SAT parallel processor designed with FPGA can solve SAT problem much faster now. And the successful design provides a foundation for the further building of dynamic SAT Parallel Processor.
出处
《深圳大学学报(理工版)》
EI
CAS
2002年第3期24-30,共7页
Journal of Shenzhen University(Science and Engineering)
基金
国家自然科学基金资助项目(69976020)