用VHDL语言实现基于布尔过程论的组合电路的设计

Boolean Process Based on VHDL Design for Combination Circuit

VHDL作为一种IEEE标准的电路硬件描述语言 ,正广泛地被电子技术人员使用。概要地介绍了布尔过程理论和VHDL标准语言 。

VHDL are widely used by electronic technology professional as IEEE standard circuit hardware description language.The paper briefly introduced the theory of Boolean process and VHDL standard language.And then we studied thier application in the design of combination circuits.