摘要
模乘器的面积过大和速度较慢是影响公钥密码体制 RSA在智能卡应用中的主要问题。文中针对 Montgomery模乘算法进行了分析和改进 ,提出了一种新的适合于智能卡应用的高基模乘器结构。由于模乘器采用两个并行 16bit乘法器和两个流水的加法器 ,使得它有效地降低了芯片面积、提高了运算速度 ,从而实现了智能卡公钥密码体制 RSA的数字签名与认证。仿真表明 :在基于华邦 0 .5μm工艺下 ,模乘器 VLSI实现共用 85 0 0个门 ,在 2 0 MHz的时钟频率下 ,加密 10 2 4bit的数据模幂乘运算平均时间仅需 3 42 ms。这个指标优于当今电子商务的加密处理器 。
The size and speed of the modular multiplier hinders the implementation of public key cryptography RSA applications for smart cards. A VLSI implementation was developed for a 1 024 bit RSA modular multiplier using a modified Montgomery algorithm. The modular multiplier was composed of two parallel multipliers and two pipelined adders, which reduced its size and greatly increased its speed. The modular multiplier has been implemented in smart cards for digit signature authentication for public key cryptography RSA. Results showed that the modular mulitiplier takes 342 ms to encrypt a 1 024 bit message on average at a clock rate of 20 MHz and holds about 8 500 gate counts.
出处
《清华大学学报(自然科学版)》
EI
CAS
CSCD
北大核心
2002年第10期1419-1422,共4页
Journal of Tsinghua University(Science and Technology)
基金
国家自然科学基金资助项目 ( 6 0 2 76 0 16 )