2.5Gbps发接器系统均衡器电路的设计

Design of Equalizer in 2.5 Gbps Transceiver System

采用片上可编程均衡技术 ,设计了用于数据率为 2 .5 Gbps发接器系统接收端的均衡器电路。电路采用 0 .1 8μm标准 CMOS工艺和 1 .8V单电源。用 UMC模型 Cadence Spectre S软件进行了仿真 ,电路在 0～1 2 5°C范围内 ,三种工艺角和电源电压变化± 1 0 %的条件下能够正确地工作。在 1 .8V电源、75°C和 tt工艺角条件下 ,电路的总功耗为 40 m W。

An equalizer circuit in receiver for 2 5 Gbps transceiver has been designed by using technique of on chip programmable equalization. The standard process of 0.18 μm CMOS and 1.8 V power supply are used. Using UMC models, the circuits are simulated by Cadence SpectreS simulators. In the range of 0～125°C, at ff, tt or ss process corner, and in the power supply range of 1.8 V±10%, the simulation results show the circuits work well and robustly. In the typical case, the total power dissipation is 40 mW.