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阈值电压对超深亚微米SRAM存储单元SNM的影响 被引量：1

Impact of Threshold Voltage on VDSM SRAM Memory Cell SNM
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摘要 采用基于物理模型的 α指数 MOSFET模型 ,对超深亚微米 (VDSM:Very Deep Submicron) SRAM存储单元的静态噪声容限 (SNM:Static Noise Margin)进行了解析分析 ,分析中考虑了随机工艺涨落造成的VDSM SRAM存储单元阈值失配对 SNM的影响 ,结果与 HSPICE仿真相符 ;文中同时分析了栅宽与 SNM的关系 ,其结论与实验结果一致 ,并给出了 VDSM The analytical Static Noise Margin (SNM) model for Very Deep Submicron (VDSM) SRAM memory cell is developed, which is based on physical α power MOSFET model. The effect of threshold voltage mismatch on SNM is analyzed, which agrees with HSPICE simulation. Meanwhile the relation of SNM and the gate width is also analyzed, which is consistent with the experiment. The design rules of VDSM SRAM memory cell are given.
作者 李文宏 章倩苓
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2002年第3期300-304,共5页 Research & Progress of SSE
关键词 阈值电压 SRAM SNM 超深亚微米 静态随机存储器 静态噪声容限 VDSM SRAM SNM
分类号 TP333.8 [自动化与计算机技术—计算机系统结构]
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参考文献10

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固体电子学研究与进展
2002年 第3期

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