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高压BCD集成电路中高压功率器件的设计研究 被引量:7

Research for Designing High Voltage Power Device in BCD HV-IC
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摘要 高压功率集成电路的设计与制造因其具有的高技术难度而极具挑战性。所谓高压功率集成电路 (HV-PIC) ,是指将需承受高电压 (需达数百伏 )的特定功率晶体管和其它低压的控制电路部分兼容 ,制作在同一块 IC芯片上。文中以器件模拟软件 Medici为工具 ,用计算机仿真的方法 ,研究了高压 BCD电路中高压功率器件的设计问题 ,其中包括器件结构、掺杂浓度、结深等主要参数及其它一些技术因素对器件耐压的影响 ,并给出了相应物理意义上的分析。根据这一设计 ,在国内进行了一块高压功率 BCD集成电路的试制 ,经测试 ,耐压超过 660伏 ,输出功率 40 W,且电路的其它器件参数达到设计值 ,IC电路整体功能正常 。 The design and manufacture of High Voltage power IC (HV PIC) face to a great challenge due to its high technique requirement. HV PIC means the combination of specific power transistors that bear very high voltage (up to several hundred volts) and the controlling circuit biased by low voltage into a monolithic IC chip. The design problems of the high voltage power device in the BCD circuits are analysed by means of computer simulation and transistor theory. The soft ware simulator Medici is used as device simulation tool. The discussion involves device structure, doping concentration, junction depth and some other technical aspects that may affect the breakdown voltage of the HV power device. Base on the proposed design principles in this paper, a typical BCD HV PIC chip is now being manufactured in a domestic fabrication line. The trial test reports that the breakdown voltage of the HV power device in this IC chip is higher than 660 V. The parameters of the all devices are correct and the IC works well.
作者 韩雁
出处 《固体电子学研究与进展》 CAS CSCD 北大核心 2002年第3期305-308,共4页 Research & Progress of SSE
基金 上海市科学技术委员会资助 项目编号为 0 170 15 0 48
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  • 1方健,易坤,李肇基,张波.高压RESURF LDMOS开态击穿模型(英文)[J].Journal of Semiconductors,2005,26(3):436-442. 被引量:2
  • 2卓伟,刘光廷,徐晓东.场板的设计和分析[J].半导体技术,1995,11(4):29-31. 被引量:2
  • 3卢豫曾.高压RESURF LDMOSFET的实现[J].电子学报,1995,23(8):10-14. 被引量:6
  • 4杨银堂,朱海刚.BCD集成电路技术的研究与进展[J].微电子学,2006,36(3):315-319. 被引量:13
  • 5关彦青,程东方,王邦麟.用TCAD进行IC新工艺的开发[J].微计算机信息,2006,22(10S):131-133. 被引量:6
  • 6Kim J,Roh T M,Kim S G,et al. High voltage power in- tegrated circuit technology using SOI for driving plasma display panels[J]. IEEE Trans Elec Dev, 2001, 48(6) : 1256-1262.
  • 7Terashima T, Yamashita J, Yamada T. Over 1000V n --ch ldmosfet and p--ch ligbt With resurf structure and mutiple floating field[C]// ISPSD, 1995. Japan, Yoko- hama, 1995.459-495.
  • 8Stephen A. Campbell: the science and engineering of mi- croelectronic fabrication[M]. Beijing, Publishing House of Electronics Industry, 2003.
  • 9Chung Y S, Baird B. Electrical-Thermal Coupling Mechanism on Operating Limit of LDMOS Transistor[C]//Proc of 2000 Internation/Eletron Devices Meeting, 2000:83- 86.
  • 10Hu C. Optimum Doping Profile for Minimum Ohmic Resistance and High Breakdown Voltage[J]. IEEE Transaction on Electron Device, 1999,26(3) :243-245.

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