摘要
集成注入逻辑器件中的控制机理是N^-N^+构成的累积层,这种累积层尚未得到适当的分析。本文的主要目的是导出N^-N^+结的J—V特性,并对N^-N^+结的累积层效应作了详细地分析。分析表明累积层效应与实验结果一致,当累积层的复合时间,τ_(s c)→0时,少子分布从注入极平面开始线性地减小,τ_(s c)→∞时,少子分布是均匀的,在有限的τ_(s c)和高偏置电平下,N^-N^+结的电流随N 中性区宽度W的增大而增大。
The controlling factor in the integrated injection logic is the N^-N^+ accumulation junction, which has never been adequately analyzed. The purpose of this pape paper is to derive the J-V characteristics of the N^-N^+ junction. The effect of the accumulation layer at the N^-N^+ junction is analyzcd in detail. It is shown that the effect of the accumlation layer at the N^-N^+ junction agrees with the experimental results. The minority carrier distribution decreases almost linearly from the injection plane if the recombination time in the accumulation layer approaches zero (τ_(sc)→0). The minority carrier distribution becomes nearly uniform for τ_(sc→∞. For finite τ_(sc), the N^-N^+ junction current increases as the width of the N^- neutral region W increases at high bias lever.
出处
《暨南大学学报(自然科学与医学版)》
CAS
CSCD
1991年第1期36-43,共8页
Journal of Jinan University(Natural Science & Medicine Edition)
基金
美国印第安诺大学资助
关键词
PNP管
螺积层效应
注入效率
Suppression factor
Effect of the accumulation layer
Injection efficiency
Poisson's equation
Epitaxial layer