Verilog HDL数字钟电路的设计研究

Research on the Design of Digital Clock Based on Verilog HDL

在Quartus II软件平台上采用电路图和文本文件相结合的方式完成数字钟电路的层次化建模,该电路具有正常显示(计时)、时间调整(校时)、闹铃、秒表等功能。整个电路最终经FPGA实验板的下载验证表明设计方案切实可行。本文通过对数字钟层次化设计的详细阐述,旨在使数字系统的学习者掌握基于FPGA的自顶而下的设计思路,又在实例设计中展现出Verilog HDL与C语言编程的不同。

A hierarchical model of digital clock circuit is designed by a block diagram file and some text files on the Quartus II software platform. The circuit design has the functions of time display and setup, time adjustment,alarm clock, and stopwatch, which proves to be practical through the downloading test of FPGA experiment plank. The paper states in detail about this design method, aiming to help the learners master the top-down hierarchical design idea based on FPGA, and learn that Verilog HDL is different from C language.