基于门节点分级选择的CMOL电路单元快速容错映射

Fast Cells Defect-Tolerant Mapping Based on Gate Node Interval Selection in CMOL Circuits

针对存在缺陷CMOL电路的单元容错映射问题,提出了一种分级选择电路门节点的容错映射方法.首先通过拓扑排序求出电路门的逻辑级;然后采用级间隔的方式进行选择,并对有缺陷连接的门节点进行惩罚,提高其被选择配置的概率.实验结果表明,与已有算法相比,该方法平均选择配置的门节点总数明显减少,在纳米二极管常开缺陷密度为40%、牺牲0.18%线长的情况下,CPU平均运行时间减少了30.68%.

For the problem of cells defect-tolerant mapping in defect existed CMOL circuits,this paper proposes adefect-tolerant mapping method based on gate node interval selection.The logic circuit is topologically sorted tocalculate the gate logic level,then interval gate nodes with defective connects are punished to improve the selectedprobability to be reallocated.The experiment results indicated that compared with the published algorithms,the proposed method shows that30.68%of CPU runtime is reduced traded with0.18%increase of wire lengthwhen the struck-open defect rate of nano-devices is up to40%.