雷达回波存储设备的信号完整性研究

Research on signal integrity of radar echo storage equipment

该文设计高速雷达回波存储系统,针对在系统设计过程中可能出现的影响信号传输完整性的诸多因素进行分析,并做出多种预防性措施。从主要器件选型、PCB板布局布线、叠层设计以及在PCB板设计制造中结合IBIS模型与Cadence仿真软件对所遇到的差分对的反射问题进行分析与研究。在重点分析差分传输线理论的基础上选取高速接口处的1组差分对提取拓扑结构,并对其在进行端接匹配前后接收的信号进行分析及眼图仿真。实验结果表明:采用ESD芯片进行端接处理后所接收的眼图波形变得整齐,抖动与尖峰明显减少。目前采取的措施可以确保实际存储设备工作的可靠性,为工程实践提供有益的借鉴。

A high-speed radar echo storage system was designed and in view of the many factors that may affect the signal transmission integrity in the system design process, a variety of preventive measures were taken. From the main component selection, PCB locating and wiring, stack design and PCB design and manufacturing, IBIS model and Cadence simulation software were combined to analyze and study the problems of signal integrity differential pair reflection encountered in the radar echo storage system. On the basis of analysis on difference transmission line theory, a group of differential pair at high-speed interface was selected to extracts its topological structure. Analysis and eye pattern simulation were conducted for the signals received before and after termination matching. Experimental results show that using ESD chip for termination processing can reduce the jitter and external noise and neat the eye pattern. These measures can ensure reliability of the actual storage device and provide a useful reference for engineering practices.