摘要
因良好的射频性能,高阻SOI(High-Resistivity Silicon-on-Insulator,HR-SOI)被广泛应用于射频集成电路(RFICs)。通过提取共面波导传输线(Co-Plane Waveguide,CPW)的射频损耗来表征衬底材料的射频性能。高阻SOI衬底由于表面寄生电导效应(Parasitic Surface Conductance,PSC),射频性能恶化。设计并制备了一种新型的改性结构来优化高阻SOI的射频性能,通过将硅离子注入到绝缘埋层中来消除表面寄生电导效应。在0~8 GHz范围内,传输线损耗优于时下业界最先进的TR-SOI的结果(Trap-Rich Layer Silicon-on-Insulator)。由于工艺简单,易于集成化,是极具潜力的射频SOI材料。
High-resistivity silicon-on-insulator(HR-SOI)is widely adopted for high performance RFICs.RF loss was measured from coplanar waveguide(CPW)transmission lines fabricated on the HR-SOI.The RF performance of HR-SOI is degenerated due to the parasitic surface conductance(PSC).In this work a novel modified structure was designed and fabricated to optimize the RF performance of HR-SOI,Si+ion was implanted into the oxide to reduce the PSC effect.The loss of the CPW is superior to the state of art TR-SOI in0-8GHz frequency.It shows the potential application for RF-SOI technology due to the simple process and easily to be integrated.
作者
程实
常永伟
魏星
费璐
CHENG Shi;CHANG Yongwei;WEI Xing;FEI Lu(State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences, Shanghai 200050, China;School of Physical Science and Technology, Shanghaitech University, Shanghai 200031,China;University of Chinese Academy of Sciences, Beijing 100049, China)
出处
《电子元件与材料》
CAS
CSCD
2017年第6期70-74,共5页
Electronic Components And Materials