嵌入广义折叠技术的集成电路测试数据压缩方案

Integrated Circuit Test Data Compression Scheme Built-in Generalized Folding Technology

针对芯片测试过程中自动测试设备需要传输大量测试数据到被测芯片,浪费了大量的测试数据传输时间的问题,提出一种广义折叠技术的集成电路测试数据压缩方案.首先构建有向图,将完全测试集映射到有向图中;其次查找有向图中最长路径,将完全测试集分割成若干个广义折叠集;最后存储广义折叠集的种子和广义折叠距离.另外,提出了广义折叠集的解压结构.理论上可以将整个测试集的存储转化成若干个广义折叠种子和广义折叠距离的存储.对部分ISCAS89标准电路中规模较大的时序电路进行实验的结果表明,在同样实验环境下,该方案在压缩效果方面优于Golomb码、FDR码、EFDR码和折叠集等成熟的压缩方法.

Due to the automatic test equipment in the process of chip need to transmit a large number of test datato the tested chip,resulting in wasting a lot of test data transmission time,an integrated circuit test data compressionscheme based on generalized folding technology is proposed.First,construct a directed graph,complete testset are mapped to the directed graph;Second,the complete test set is divided into several generalized folding setby find the longest paths;Finally,store the generalized folding set seeds and generalized folding distance.In addition,the decompression structure of generalized folding set is proposed.In theory,the storage of the whole testset can be the storage of some generalized folding seeds and distance.Experimental results on part of theISCAS89benchmark circuits show that,under the same experimental conditions the compression effect is betterthan that of Golomb coding,FDR coding,EFDR coding and the fold set mature compression method.