高速串行误码测试仪设计与实现

Design and Implementation of High Speed Serial Bit Error Rate Tester

针对高速串行传输系统测试误码率的需求,设计实现了一种串行误码测试仪。采用了FPGA并行序列图形发生,高速串并/并串转换电路和模块化程序的设计思路,具有测试速率快、速率连续可变和测试图形种类多的特点。测试结果表明:该系统测试速率达100Mb/s^12.5Gb/s,支持PRBS和可编程数据等测试图形,具有良好的性能。

For the requirement of bit error rate(BER)testing of high speed serial transmission,a High Speed Serial Bit Error Rate Tester(BERT)is designed and realized.The BERT adopts parallel sequence pattern generation of filed programmable gate array(FPGA),high speed serializer/deserializer and modularized program,which leads to fast continuously variable rate and many kinds of test pattern property.Experiments show that the system has good performance which supports PRBS and other programmable data test pattern with testing rate from100Mb/s to12.5Gb/s.